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PRELIMINARY
CY28358
200-MHz Differential Clock Buffer/Driver
Features
* Up to 200 MHz operation * Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications * Distributes one clock input to six differential outputs * External feedback pin FBIN is used to synchronize the outputs to the clock input * Conforms to the DDR1 specification * Spread AwareTM for EMI reduction * 28-pin SSOP package
Description
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential output levels. This device is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one feedback clock output FBOUT. The clock outputs are controlled by the input clock CLKIN and the feedback clock FBIN. The two line serial bus can set each output clock pair (CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clock CLKIN and the feedback clock FBIN to provide high-performance, low-skew, low-jitter output differential clocks.
Block Diagram
Pin Configuration
10
SCLK SDATA
Serial Interface Logic
CLKT2 CLKC2 CLKT3 CLKC3
CLKIN NC AVDD AGND VDD CLKT2 CLKC2
CY28358
CLKT0 CLKC0 CLKT1 CLKC1
CLKC0 CLKT0 VDD CLKT1 CLKC1 GND SCLK
CLKIN PLL FBIN
CLKT4 CLKC4 CLKT5 CLKC5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND CLKC5 CLKT5 CLKC4 CLKT4 VDD SDATA NC FBIN FBOUT NC CLKT3 CLKC3 GND
AVDD
FBOUT
28 pin SSOP
Cypress Semiconductor Corporation Document #: 38-07417 Rev. *A
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 14, 2002
PRELIMINARY
Pin Description[1]
Pin 8 20 2,4,13,17,24,26 1,5,14,16,25,27 19 Name CLKIN FBIN CLKT(0:5) CLKC(0:5) FBOUT I/O I I O O O Clock Input. Feedback Clock Input. Connect to FBOUT for accessing the PLL. Clock Outputs Clock Outputs Feedback Clock Output. Connect to FBIN for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Serial Clock Input. Clocks data at SDATA into the internal register. Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 2.5V Power Supply for Logic 2.5V Power Supply for PLL Ground Analog Ground for PLL Not Connected Output Description
CY28358
Electrical Characteristics Input Input Differential Outputs
7 22
SCLK SDATA
I I/O
Data Input for the two line serial bus Data Input and Output for the two line serial bus
3,12,23 10 6,15,28 11 9, 18, 21
VDD AVDD GND AGND NC
2.5V Nominal 2.5V Nominal
Function Table
Inputs VDDA GND GND 2.5V 2.5V 2.5V CLKIN L H L H < 20 MHz CLKT(0:5)[2] L H L H Hi-Z Outputs CLKC(0:5)[2] H L H L Hi-Z FBOUT L H L H Hi-Z PLL BYPASSED/OFF BYPASSED/OFF On On Off
Zero Delay Buffer
When used as a zero delay buffer the CY28358 will likely be in a nested clock tree application. For these applications the CY28358 offers a clock input as a PLL reference. The CY28358 then can lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs.
When VDDA is strapped LOW, the PLL is turned off and bypassed for test purposes.
Power Management
The individual output enable/disable control of the CY28358 allows the user to implement unique power management schemes into the design. Outputs are three-stated when disabled through the two-line interface as individual bits are set low in Byte0 and Byte1 registers. The feedback output FBOUT cannot be disabled via two line serial bus. The enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial "runt" clocks.
Notes: 1. A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. 2. Each output pair can be three-stated via the two line serial interface.
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PRELIMINARY
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions.
T
CY28358
Data Protocol
The clock driver serial protocol accepts block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The block write and block read protocol is outlined in Table 1. The slave receiver address is 11010010 (D2h).
Table 1. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave ...................... Data Byte (N-1) - 8 bits Acknowledge from slave Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop Block Read Protocol Description
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PRELIMINARY
Byte0: Output Register1 (1 = Enable, 0 = Disable) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 24, 25 13, 14 26, 27 Pin# 2, 1 4, 5 CLKT0, CLKC0 CLKT1, CLKC1 Reserved Reserved CLKT2, CLKC2 CLKT5, CLKC5 Reserved CLKT4, CLKC4 Description
CY28358
Byte1: Output Register 2 (1 = Enable, 0 = Disable) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 0 0 0 0 17, 16 Pin# Reserved CLKT3, CLKC3 Reserved Reserved Reserved Reserved Reserved Reserved Description
Byte2: Test Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
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PRELIMINARY
Parameter Measurement Information
CLKIN
1.25V 1.25V
CY28358
FBIN
1.25V 1.25V
t()n
t()n+1
t()n =
n1=N
N
t()n
(N is large number of samples)
Figure 1. Static Phase Offset
CLKIN
1.25V 1.25V
FBIN
td()
t()
td()
td()
t( )
td()
Figure 2. Dynamic Phase Offset
CLKT[0:5], FBOUT CLKC[0:5] CLKT[0:5], FBOUT CLKC[0:5]
tsk(o)
Figure 3. Output Skew
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PRELIMINARY
CY28358
CLKT[0:5], FBOUT CLKC[0:5]
tc(n)
CLKT[0:5], FBOUT CLKC[0:5]
1 f(o) tjit(hper) = tc(n) - 1 fo
Figure 4. Period Jitter
CLKT[0:5], FBOUT CLKC[0:5]
t(hper_n) 1 f(o)
t(hper_N+1)
t jit(hper) = thper(n) - 1 2x fo
Figure 5. Half-Period Jitter
CLKT[0:5], FBOUT CLKC[0:5]
t c(n)
t c(n)
t jit(cc) = t c(n) - t c(n+1)
Figure 6. Cycle-to-cycle Jitter
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PRELIMINARY
CY28358
T PCB CLKT
16 pF
M easurem ent Point
CLKIN 50 CLKC FBIN 50 FBOUT T PCB
100 M easurem ent Point
16 pF
Figure 7. Differential Signal Using Direct Termination Resistor
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PRELIMINARY
Maximum Ratings[3]
Input Voltage Relative to VSS:...............................VSS - 0.3V Input Voltage Relative to VDDQ or AVDD:.............. VDD + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature: .................................... 0C to +85C Maximum Power Supply: ................................................3.5V
CY28358
This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
DC Parameters[4] (VDDA = VDDQ = 2.5V + 5%, TA = 0C to +70C)
Parameter VIL VIH VIL VIH IIN IOL IOH VOL VOH VOUT VOC IOZ IDDQ IDSTAT IDD CIN Description Input Low Voltage Input High Voltage Input Voltage Low Input Voltage High Input Current Output Low Current Output High Current Output Low Voltage Output High Voltage Output Voltage Swing[5} Output Crossing Voltage[6] High-Impedance Output Current Dynamic Supply Current[7] Static Supply Current PLL Supply Current Input Pin Capacitance VDDA only 9 4 VO = GND or VO = VDDQ All VDDQ and VDDI, FO = 200 MHz Conditions SDATA, SCLK SDATA, SCLK CLKIN, FBIN CLKIN, FBIN VIN = 0V or VIN = VDDQ, CLKIN, FBIN VDDQ = 2.375V, VOUT = 1.2V VDDQ = 2.375V, VOUT = 1V VDDQ = 2.375V, IOL = 12 mA VDDQ = 2.375V, IOH = -12 mA 1.7 1.1 (VDDQ/2) - 0.2 -10 235 VDDQ/2 VDDQ-0.4 (VDDQ/2) + 0.2 10 300 2 12 6 2.1 -10 26 -18 35 -32 0.6 10 2.2 0.4 Min. Typ. Max. 1.0 Unit V V V V A mA mA V V V V A mA mA mA pF
Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. Unused inputs must be held high or low to prevent them from floating 5. For load conditions see Figure 7. 6. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120 resistor. See Figure 7. 7. All outputs switching loaded with 16pF in 60 environment. SeeFigure 7
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PRELIMINARY
AC Parameters[8,9] (VDD = VDDQ = 2.5V5%, TA = 0C to +70C)
Parameter fCLK tDC tLOCK tR/tF tPZL,tPZH tPLZ,tPHZ tCCJ tjit(h-per) tPLH tPHL tSKEW tPHASE tPHASEJ Description Operating Clock Frequency Input Clock Duty Cycle Maximum PLL lock Time Output Clocks Slew Rate Output Enable Time[10] (all outputs) Output Disable Time[10] (all outputs) Cycle to Cycle Jitter[12] Half-period jitter[12] Low-to-High Propagation Delay, CLKIN to CLKT[0:5] High-to-Low Propagation Delay, CLKIN to CLKT[0:5] Any Output to Any Output Skew[11] Phase Error[11] f > 66 MHz -150 -50 Phase Error Jitter f > 66 MHz f > 66 MHz -100 -100 1.5 1.5 3.5 3.5 20% to 80% of VOD 1 3 3 Conditions Min. 60 40 Typ.
CY28358
Max. 200 60 100 2.5
Unit MHz % s V/ns ns ns
100 100 6 6 100 150 50
ps ps ns ns ps ps ps
Notes: 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. 9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30kHz and 33.3kHz with a down spread of -0.5%. 10. Refers to transition of non-inverting outpu.t 11. All differential input and output terminals are terminated with 120/16pF as shown in Figure 7. 12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
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PRELIMINARY
Ordering Information
Part Number CY28358OC CY28358OCT Package Type 28-Pin SSOP 28-Pin SSOP -Tape and Reel
CY28358
Product Flow Commercial, 0 to 70C Commercial, 0 to 70C
Package Drawing and Dimensions
28-Lead (5.3 mm) Shrunk Small Outline Package O28
51-85079-*C
Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges..
PRELIMINARY
Document History Page
Document Title: CY28358 200-MHz Differential Clock Buffer/Driver Document #: 38-07417 REV. ** *A ECN NO. 118004 122925 Issue Date 09/11/02 12/14/02 Orig. of Change INA RBI New Data Sheet Description of Change
CY28358
Add power up requirements to operating condicitons information.
Document #: 38-07417 Rev. *A
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